Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.