A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. The test vehicle incorporates a self-timed or gated speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program data logs from scan flip flops. One embodiment incorporates a gated clock in the gated speed circuit producing gated data that delivers greater statistical properties with respect to Integrated Circuit Direct Drain Quiescent Current (IDDQ) testing.