A system includes a core chipset that is configured to communicate with a central processing unit. The system includes a memory bridge configured to communicate with memory. An accelerated graphics processor configured to communicate with a graphics device. An input/output bridge communicates with the memory bridge and the accelerated graphics processor and includes a bus controller. A Peripheral Component Interconnect-Extended (PCI-X) bus communicates with the bus controller. An integrated circuit includes a bus interface that communicates with the PCI-X bus. An Ethernet controller communicates with the bus interface. A serial advanced technology attachment (ATA) host adapter communicates with the bus interface and is configured to control a mass data storage unit.