Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.