Systems and methods are disclosed herein to provide improved verification of flash memory erasure. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an array of flash memory cells. A plurality of sense amplifiers are also provided wherein each sense amplifier is associated with a plurality of the flash memory cells and adapted to detect a state of one of the associated flash memory cells selected from the plurality of flash memory cells. A first logic circuit is also provided to receive the states of the selected flash memory cells from the sense amplifiers and perform a first logic operation at approximately the same time on the states to verify that all states of the selected flash memory cells correspond to an erased state.