Data transmission for writing data into a shared memory is performed by a high-speed dedicated line provided between each processor and the shared memory. When a processor performs writing to a shared memory space, the processor notifies an update notification bus corresponding to the conventional global bus, to which address the update is to be performed. The other processors which have detected this notification inhibit access to that address and wait for the write data to be sent to the address via the dedicated line. When the data has arrived, the data is written into the corresponding address. Here, the data is also written into the corresponding address, thereby maintaining the cache coherency. Moreover, when transmitting a write address, it is necessary to acquire the bus use right while data transmission is performed by using the dedicated line, which significantly reduces the time required for acquiring the bus use right.