In the conventional manufacture method that has reduced the number of manufacture processes by forming semiconductor layers and source-drain wires for a channel-etch type insulating gate transistor in a single photo etching process using halftone exposure technology, the channel length increases when the photosensitive resin pattern used at above formation process of source-drain patterning is reduced. Hence the manufacture tolerance (margin) is small, and the yield decreases when the distance between the source wire and drain wire is shortened. This invention suggests the 4-mask process and 3-mask process of the TN type liquid crystal display devices and IPS-type liquid crystal display devices by combining the following: streamline technology to form the already known pixel electrodes and scanning lines simultaneously; new technology to streamline the opening formation process in gate insulating layers and island formation process of semiconductor layer, using halftone exposure technology; and new technology to streamline the protective layer formation process for electrode terminals by adding halftone exposure technology to the already known anode oxidization technology for source-drain wires.