Computer technology supports multiple byte order formats, separately or simultaneously. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. The PAT has a plurality of entries. Each entry indicates a memory type and a byte order format for a physical address, wherein a plurality of attribute bits and a virtual address are associated with the physical address. A portion of the attribute bits are utilized to select one of the entries. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format. The MTRR is configured to indicate a memory type and a byte order format for a range of physical addresses, wherein the memory type and range register (MTRR) receives a physical address and provides a corresponding memory type and a corresponding byte order format.