A method is taught for increasing the steady-state verification speed of analog and mixed signal design through increased simulation speed, model abstraction by probing an existing component model or actual device and formal comparison of distinct component models.The innovative method taught here incrementally generates processor instructions optimized for operating the analog solver around a specific set of values (the operating context), caches sequences and applies the currently applicable operating context at each point in the simulation.The invention discloses a method for semi-automatically generating a mixed-signal or analog model based on iterative probing of an existing device or behavioral simulation.The invention teaches a method for model abstraction to alter the level of detail present in a running simulation. A means for graphically evaluating the match quality constitutes the final innovative step.The innovative method for the formal comparison of two analog or mixed signal models within a prescribed operating range for each interface between the model and its environment without the need for exhaustive simulation.