A method of manufacturing a semiconductor device comprising a dual gate
field effect transistor is disclosed, in which method a semiconductor
body with a surface and of silicon is provided with a source region and a
drain region of a first conductivity type and with a channel region of a
second conductivity type, opposite to the first conductivity type,
between the source region and the drain region and with a first gate
region separated from the channel region by a first gate dielectric and
situated on one side of the channel region and with a second gate region
separated from the channel region by a second gate dielectric and
situated on an opposite side of the channel region, and wherein both gate
regions are formed within a trench formed in the semiconductor body.