A DLL includes a control module coupled with a phase detect signal. The phase detect signal is used by a control module to generate feedback and output select signals. The feedback and output select signals are each coupled to a multiplexer. Each multiplexer is coupled to a Multi-Tap Delay Line (MTDL). The MTDL provides a plurality of delayed signals that are selectable by the two multiplexers. The first multiplexer, coupled to the feedback select signal, selects a feedback clock signal. The second multiplexer, coupled to the output select signal, select a DLL output signal. The control module may receive other signals, such as a delay select signal, that may be used to program or set the delay of the output signal. In addition, a plurality of output signals may be available from the DLL.