A semiconductor device including: a DRAM which is a volatile memory; a PLL circuit which outputs an operation clock signal generated by multiplying an input clock signal; a circuit block which operates in synchronization with the operation clock signal; first and second refresh controllers for requesting a refresh operation of the DRAM; and a memory controller which arbitrates between an access request for the DRAM from the circuit block and a refresh request from the first refresh controller. In a first mode in which the PLL circuit operates, the first refresh controller issues the refresh request to the DRAM controller. In a second mode in which the operation of the PLL circuit stops, the second refresh controller issues the refresh request, the refresh request bypassing the DRAM controller.