A processor clock control device operable to control a plurality of clock
signals output to a processor, said processor comprising a plurality of
domains each clocked by a respective one of said plurality of clock
signals, said processor being operable in different modes including a
functional mode and a test mode, said processor clock control device
comprising: a clock signal input operable to receive a slower reference
clock signal or a higher speed operational clock signal; at least two
clock signal outputs each operable to output a clock signal to a
respective domain of said processor; a mode control signal input operable
to receive a mode control signal indicating a mode of operation of said
processor; a launch control signal input operable to receive a launch
control signal, said launch control signal indicating portions of said
processor to be tested; and an initiation signal input operable to
receive an initiation signal indicating initiation of a processor test;
wherein said processor clock control device is operable: in response to
receipt of a test mode signal at said mode control signal input to
receive a reference clock at said clock signal input and to output said
reference clock at at least one of said plurality of clock signal
outputs; and in response to a predetermined launch control signal
received at said launch control signal input, said predetermined launch
control signal indicating testing of a path between one of said clocked
domains clocked by one of said clock signal outputs and one other of said
clocked domains clocked by one other of said clock signal outputs, and
following receipt of said initiation signal, to independently control
said plurality of clock signal outputs such that at least one launch
clock pulse is output from said one of said clock signal outputs while
said one other of said clock signal outputs is suppressed, and following
this to output at least one capture clock pulse from said one other of
said clock signal outputs while said one of said plurality of clock
signal outputs is suppressed.