A processor (1700) including a pipeline (1710, 1740) having a fetch
pipeline (1710) with branch prediction circuitry (1840) to supply
respective predicted taken target addresses for branch instructions, an
execution pipeline (1740) with a branch execution circuit (1870), and
storage elements (in 1860) and control logic (2350) operable to establish
a first-in-first-out (FIFO) circuit (1860) with a write pointer WP1 and a
read pointer RP1. The control logic (2350) is responsive to the branch
prediction circuitry (1840) to write a predicted taken target address to
a storage element (in 1860) identified by the write pointer (WP1) and the
predicted taken target address remains stationary therein. The FIFO
circuit (1860) bypasses a plurality of pipestages between the branch
prediction circuitry (1840) and the branch execution circuit (1870). The
control logic (2350) is operable to read a predicted taken target address
(PTTPCA) from a storage element (in 1860) identified by the read pointer
RP1.