A processor is responsive to a thermistor temperature (T.sub.th) adjacent a FET and to a drain-to-source voltage (V.sub.DS) of the FET. The processor stores the characteristics of the PET and a thermal model of the system hardware and uses a first set of equations to determine the temperature (T.sub.J) at the junction of the PET in a stable region of operation where T.sub.J-T.sub.th is nearly constant. The processor is further responsive to a step change in successive measurements of V.sub.DS indicative of a lag of T.sub.th relative to T.sub.J. In this step-change region, the processor then resolves T.sub.J based upon a second set of equations.