A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.