A data time difference absorbing circuit comprises a memory (36) in which first digital data containing first time reference code data are stored and from which the first digital data are read, a memory (37) in which second digital data containing second time reference code data are stored and from which the second digital data are read, a timing data detecting portion (41) for detecting the first time reference code data contained in the first digital data read from the memory (36) and the second time reference code data contained in the second digital data read from the memory (37), a phase difference detecting portion (42) for detecting a phase difference between the first and second time reference code data, and a control signal producing portion (40) operative to control at least one of a timing at which the first digital data are read from the memory (36) and a timing at which the second digital data are read from the memory (37) in response to the phase difference detected by the phase difference detecting portion (42) so as to keep a condition in which the phase difference detected by the phase difference detecting portion (42) is substantially zero.