The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprising an uppermost portion 142 of the porous silicon-based dielectric layer.

 
Web www.patentalert.com

< Annealing process and device of semiconductor wafer

> Cross-fill pattern for metal fill levels, power supply filtering, and analog circuit shielding

~ 00416