A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is executed in the integer processing unit alone. The second instruction format includes instructions for the integer processing unit and the data processing unit, the second instructions being executed in both the integer processing unit and the data processing unit in parallel. When an instruction in the first instruction format is to be executed, only in the integer processing unit, a control signal is generated in the integer processing unit and is supplied to the data processing unit to halt an operation of the data processing unit.