A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are "close" (i.e., within a specified tolerance) may be combined into a single table or matrix.