This device includes a camera, a host module, an interface part, and a chassis, wherein the host module has a host CPU that is connected to the interface, the camera module has a register that is provided with a first area and a second area distinguished from the first area depending on the address, and a camera CPU that receives the interruption when the data is written in the first area, the host CPU prepares a type of data and writes it in the first area, the camera CPU prepares dual data that correspond to the written type of data and writes it in the second area, and the host CPU can directly read the data from the second area while designating the address of the second area and further, the host CPU can directly write the data in the second area while designating the address of the second area.