A pattern-dependent model is used to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) a lithography or etch process, and an impact is determined of the variations of feature dimensions on electrical characteristics of the integrated circuit. An impact is determined of the topological variations on electrical characteristics of the integrated circuit. An RC extraction tool is used in conjunction with the using of the model and the determining of the impact.