A system and method is provided for processing a first instruction set and
a second instruction set in a single processor. The method includes
storing a plurality of instructions of the second instruction set in a
plurality of buffers proximate to a plurality of execution units,
executing an instruction of the first instruction set in response to a
first counter, and executing at least one instruction of the second
instruction set in response to at least a second counter, wherein the
second counter is invoked by a branch instruction of the first
instruction set.