A hardware model conversion system includes a logic synthesis tool and a hardware model conversion program. The logic synthesis tool logically synthesizes an HDL-described circuit and then outputs intermediate data. One assign statement described in the intermediate data is associated with one assign cell. The hardware model conversion program creates a logical structure table that shows a circuit connection relationship between the plural assign cells. The hardware model conversion program refers to the logical structure table and executes model conversion of the HDL-described circuit to a pipeline structure so that assign cells having the same logic depth will belong to the same pipeline stage.