An FPGA equivalent of a structured ASIC implementation of a user's logic design is produced by taking advantage of various aspects of the way in which the structured ASIC implementation was produced. For example, the structured ASIC breaks the user's logic design down into blocks that are readily implemented in basic units of the FPGA circuitry. Starting from such an acceptable ASIC mapping of the user's logic, resynthesis for FPGA implementation can be performed, at least as a first step, on a block-by-block basis. The FPGA implementation can then be made more economical and efficient by looking for blocks that can be combined in individual basic units of the FPGA circuitry.