A memory system and a set of user-level instructions that are callable from user-level code for converting virtual addresses to physical addresses and conveying the physical addresses to peripheral devices without requiring a system call. The system uses a translation look-aside buffer (TLB) implemented in a microprocessor. The contents of the TLB can be updated while processes are executing, allowing for virtual/physical addresses to be constantly updated and loaded into the buffer without requiring that the buffer be too large. Pages in use per transaction or user-level job are "pinned down" and pinned page counts per transaction or user-level job, as well as overall counts are maintained.

 
Web www.patentalert.com

< Computer platform memory access control method and system with memory configuration automatic setting capability

> Two address map for transactions between an X-bit processor and a Y-bit wide memory

~ 00426