A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test. The receiver capable of executing control so as to make a phase of the input data coincide with that of a recovery clock.