A method of modeling a design in a high level modeling system that
supports unidirectional data flow, may comprise identifying a bus-block
to represent a connectivity of a bi-directional bus in an system. The
bus-block may be represented in serial relationship with the bus. Taps
may interface the bus via the bus-block. During simulation, the bus-block
emulates behavior of a tri-state buffer in series with an input line for
the tap interface. During synthesis, pairs of unidirectional input and
output lines of opposite data-routing orientation, which may emulate bus
ports to the bus-block, may be collapsed to a single bus port. The
synthesis may further generate a netlist that may dispose a tri-state
buffer between a tap input and the bus. The netlist may also represent
layout of the tri-state buffer for driving an output of the tap.