A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating path for combinations of cell patterns; selecting a combination of cell patterns, based on lengths of the calculated delay times and the allowable delay time; and generating layout data of the signal propagating path using the selected combination.