A single chip display processor comprised of a dynamic random access
memory (DRAM) for storing at least one of graphics and video pixel data,
a pixel data unit (PDU) for processing the pixel data, integrated in the
same integrated circuit (IC) chip as the DRAM, the IC chip further
comprising a massively parallel bus for transferring blocks of pixel data
at the same time from the DRAM to the PDU, whereby the PDU can process
the blocks of pixel data for subsequent display of processed pixel data.