A multiple integrated circuit chip structure provides interchip
communication between integrated circuit chips of the structure with no
ESD protection circuits and no input/output circuitry. The interchip
communication is between internal circuits of the integrated circuit
chips. The multiple integrated circuit chip structure has an interchip
interface circuit to selectively connect internal circuits of the
integrated circuits to test interface circuits having ESD protection
circuits and input/output circuitry designed to communicate with external
test systems during test and burn-in procedures. The multiple
interconnected integrated circuit chip structure has a first integrated
circuit chip mounted to one or more second integrated circuit chips to
physically and electrically connect the integrated circuit chips to one
another. The first integrated circuit chips have interchip interface
circuits connected each other to selectively communicate between internal
circuits of the each other integrated circuit chips or test interface
circuits, connected to the internal circuits of each integrated circuit
chip to provide stimulus and response to said internal circuits during
testing procedures. A mode selector receives a signal external to the
chip to determine whether the communication is to be with one of the
other connected integrated circuit chips or in single chip mode, such as
with the test interface circuits. ESD protection is added to the mode
selector circuitry.