The present invention provides a processor which has a small-scale circuit
and is capable of executing loop processing at a high speed while
consuming a small amount of power. When the processor decodes an
instruction "jloop C6,C1:C4,TAR,Ra", the processor (i) sets a conditional
flag C4 to 0 when the value of a register Ra is smaller than 0, (ii)
moves the value of a conditional flag C2 to a conditional flag C1, moves
the value of a conditional flag C3 to the conditional flag C2, and moves
the value of the conditional flag C4 to the conditional flags C3 and C6,
(iii) adds -1 to the register Ra and stores the result into the register
Ra, and (iv) branches to an address specified by a branch register (TAR).
When not filled with a branch target instruction, the jump buffer will be
filled with a branch target instruction.