A parallel A/D converter includes a plurality of comparators for comparing an input signal in parallel, an input signal line for distributing the input signal to the plurality of comparators, and a sampling clock distributor for distributing sampling clock for sampling the input signal to the plurality of comparators at a distribution timing determined according to delay of the input signal due to the input signal line.

 
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> Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity

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