A system-on-chip (SoC) integrated circuit including an interleaved
delta-sigma analog to digital converter (ADC) provides for reduced noise
in the ADC conversions. The ADC is operated intermittently and the
balance of the digital circuits forming the system are halted while the
conversions take place. The halted portion of the system may include an
output low-pass filter of the ADC. The system may include a processor
core or other logic having a clock frequency unrelated to the ADC
modulator clock frequency that is not otherwise clock-managed to reduce
noise induced in the converter output by the operation of the core or
other logic.