In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit coupled to the instruction cache. Each of the plurality of instruction buffers is configured to store instructions fetched from a respective thread of a plurality of threads. The cache miss unit is configured to monitor cache misses in the instruction cache. Particularly, the cache miss unit is configured to detect which of the plurality of threads experience a cache miss to a cache line. Responsive to a return of the cache line for storage in the instruction cache, the cache miss unit is configured to concurrently cause at least one instruction from the cache line to be stored in each of the plurality of instruction buffers that corresponds to one of the plurality of threads which experienced the cache miss to the cache line.