A pipeline accelerator includes a bus and a plurality of pipeline units,
each unit coupled to the bus and including at least one respective
hardwired-pipeline circuit. By including a plurality of pipeline units in
the pipeline accelerator, one can increase the accelerator's
data-processing performance as compared to a single-pipeline-unit
accelerator. Furthermore, by designing the pipeline units so that they
communicate via a common bus, one can alter the number of pipeline units,
and thus alter the configuration and functionality of the accelerator, by
merely coupling or uncoupling pipeline units to or from the bus. This
eliminates the need to design or redesign the pipeline-unit interfaces
each time one alters one of the pipeline units or alters the number of
pipeline units within the accelerator.