A semiconductor memory device includes plural memory cells MC arranged in a matrix, plural bit lines BL and plural plate line voltage supply lines SCP which are arranged in a row direction, plural sense amplifier circuits SA which are arranged in a column direction and are electrically connected to the respective bit lines, plural plate line voltage supply circuits CPD which are arranged in the column direction and drive the plate line voltage supply lines SCP, and means for electrically connecting the plate line voltage supply lines SCP with the plural plate lines CP, wherein the respective plate voltage supply lines SCP are electrically connected, at different positions on the same plate line CP, to the plate line CP.