Provided are a memory controller that selectively changes a frequency of a memory clock signal, a smart card including the memory controller, and a method of controlling a read operation of a memory. The memory controller includes a central processing unit (CPU), a memory interface, and a frequency change controller. The CPU outputs a read command signal in response to a data read request signal and outputs a write command signal in response to a data write request signal. The memory interface outputs a plurality of control signals in response to one of the read command signal and the write command signal, generates a memory clock signal based on a system clock signal, and changes a frequency of the memory clock signal in response to a frequency change control signal. The frequency change controller outputs the frequency change control signal in response to the plurality of control signals and the memory clock signal. The memory controller, the smart card including the memory controller, and the method of controlling a read operation of a memory prevent the memory from outputting erroneous data when the memory is operated at a high frequency.