A memory unit that is capable of operating in a desired operation condition with less power consumption, and a semiconductor device using the memory unit. The memory circuit comprises a cell array in which a plurality of memory cells is arranged, a driver circuit, a plurality of selection circuits each of which includes a memory circuit, and a power source circuit. A plurality of potentials is supplied to each of plurality of selection circuits from the power source circuit, each of plurality of selection circuits selects a potential among the plurality of potentials in accordance with data stored in each memory circuit, and the selected potential is supplied to a memory cell corresponding to each of the plurality of selection circuits among the plurality of memory cells by a signal output from the driver circuit.