A method for providing endianness control in a data processing system
includes initiating an access which accesses a peripheral, providing a
first endianness control that corresponds to the peripheral, and
completing the access using the endianness control to affect the
endianness order of the information transferred during the access. In one
embodiment, the first endianness control overrides a default endianness
corresponding to the access. The default endianness may be provided by a
master endianness control corresponding to a master requesting the
current access. A data processing system includes a first bus master,
first and second peripherals, first endianness control corresponding to
the first peripheral and second endianness control corresponding to the
second peripheral, and control circuitry which uses the first endianness
control to control endianness for an access between the first bus master
and the first peripheral. In one embodiment, the data processing system
may include multiple masters.