A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

 
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> Ferroelectric memory devices having a plate line control circuit

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