The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words, and transferring the main code words to one of a plurality of memory banks. The semiconductor device also includes a data output portion for receiving one page worth of data, including main code words transferred from the data latch circuit, correcting errors in the data when the data includes fewer than a predetermined number of errors for each main code word, adding the error information to each read code word, and outputting the result.