One embodiment of the present invention provides a system that samples
instructions on a processor that supports speculative-execution. The
system starts by selecting an instruction, wherein selecting an
instruction involves selecting an instruction that is received from an
instruction fetch unit or a deferred queue, wherein the deferred queue
holds deferred instructions which are deferred because of an unresolved
data dependency. The system then records information about the selected
instruction during execution of the selected instruction, whereby the
recorded information can be used to determine the performance of the
processor.