Gated clock signals in ASIC designs are automatically optimized for implementation with a programmable device. Components having gated clock signals are identified and converted to operate directly from the base clock signal. To maintain compatibility, the data signal to the component is modified to connect with additional input logic responsive to a clock enable signal. The input logic modifies the signal received by the component's data input so that the component's output in response to the clock enable signal is unchanged. To this end, a system and method may identify the logic cone associated with a gated clock signal, convert this logic cone into a Boolean expression, and determine cofactors of the base clock signal from this Boolean expression. The input logic and clock enable logic are derived from an analysis of the cofactors of the base clock signal.