A method for verifying performance of an array by simulating operation of
edge cells in a full array model reduces the computation time required
for complete design verification. The edge cells of the array (or each
subarray if the array is partitioned) are subjected to a timing
simulation while the center cells of the array are logically disabled,
but remain in the circuit model, providing proper loading. Additional
cells are specified for simulation if calculations indicate a worst-case
condition due to a non-edge cell. Wordline arrivals are observed to
determine worst-case rows for selection. For write operations, the
difference between the wordline edges and the data edges is used to
locate any non-edge "outlier" cells. For read operations, the wordline
delays are summed with the bitline delays determined from edge column
data to locate any outliers.