In a data input/output with other apparatus, a data transfer controller (DTC) of a storage controller multiprocesses a data transfer with the other apparatus by utilizing a saving/recovering operation and suppresses a load therefrom, thereby improving performance thereof. A first storage apparatus includes two DMA units in a data transfer LSI of the DTC, uses them to process one or more data transfers concurrently, uses the saving or recovering operation to a memory #3 also in one DMA unit to process the data transfer while the data transfers are switched, thereby multiprocessing a plurality of data transfers. Based on an instruction from the IOC, the DTC makes one of the DMA units recover the necessary data transfer information and data from the memory #3 and transfer the data to the memory, and concurrently the other of the DMA units, which is not processed presently, save in advance, to the memory #3, the data transfer information and the data stored in the memory.