A server computer system receives error data including a physical memory
address along with configuration data associated with the physical memory
address, and may also include error syndrome data. The server computer
system includes a memory error decoder component that is operable to
process the physical memory address and configuration data to generate a
memory bus address corresponding to the physical memory address. The
memory error decoder also processes the error syndrome data to generate
the location of an erroneous bit within a group of data bits and all
possible electrical routes of the erroneous data bit within a failing
computer system. The server system outputs the memory bus address and the
location and electrical route of the erroneous data bit.