A mixed-mode signal processor architecture provides decision feedback equalization for a communications channel. A decision circuit compares an analog signal to a predetermined threshold and outputs a digital signal based on the comparison. A mixed-mode decision feedback equalizer (DFE) includes a plurality of tap weights and produces a DFE signal using the analog signal, the digital signal, and the tap weights. A first summer has a first input that communicates with an input of the decision circuit, a second input that communicates with an output of the decision circuit, and an output. An adaptation circuit communicates with the output of the first summer and adjusts the tap weights of the mixed-mode DFE, the clock signal a timing of the clock signal of a PLL, and an automatic gain control signal of an amplifier.