A first phase-locked loop (PLL) circuit includes an input for receiving a
timing reference signal from an oscillator, a controllable oscillator
circuit supplying an oscillator output signal, and a multi-modulus
feedback divider circuit. A second control loop circuit is selectably
coupled through a select circuit to supply a digital control value (M) to
the multi-modulus feedback divider circuit of the first loop circuit to
thereby control the oscillator output signal. While the second control
loop is coupled to supply the control value to the feedback divider
circuit, the control value is determined according to a detected
difference between the oscillator output signal and a reference signal
coupled to the second control loop circuit at a divider circuit. While
the second control loop circuit is not coupled to control the first PLL
circuit, the first PLL circuit receives a digital control value to
control a divide ratio of the feedback divider, the digital control value
is determined at least in part according to a stored control value stored
in nonvolatile storage, the stored control value corresponding to a
desired frequency of the oscillator output signal.