The invention relates to a tri-type memory device comprising a compression mechanism. According to the invention, the memory stores binary patterns that are associated with respective references. Data chains are analyzed by successive section of K bits (K>1) in order to extract one of the references when there is a match with a stored binary pattern associated with said reference. The memory is organized into several successive memory cell states, the analysis of the (i+1)-th section of a chain providing access to a cell of stage i.gtoreq.0. Each non-empty cell of a stage i.gtoreq.0 contains one of the following: a register-type analysis tracking pointer designating a register of 2.sup.K cells of stage i+1; a linear-type analysis tracking pointer designating a zone of one or two cells forming a reduced register of stage i+1; or a reference associated with a stored binary pattern.